/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2023 Intel Corporation. All rights reserved
 *
 */

void socfpga_init_smmu(void);
#define SOCFPGA_NEXT_TBU_PERIPHERAL	4
/* DMA0 STREAMID */
#define SYSMGR_DMA0_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x17C
/* DMA1 STREAMID */
#define SYSMGR_DMA1_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x180
/* SDM  STREAMID */
#define SYSMGR_SDM_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x184
/* USB2 STREAMID */
#define SYSMGR_USB2_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x188
/* USB3 STREAMID, FUTURE USE */
#define SYSMGR_USB3_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x18C
/* SDMMC STREAMID */
#define SYSMGR_SDMMC_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x190
/* NAND STREAMID */
#define SYSMGR_NAND_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x194
/* ETR STREAMID */
#define SYSMGR_ETR_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x198
/* TSN0 STREAMID */
#define SYSMGR_TSN0_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x19C
/* TSN1 STREAMID */
#define SYSMGR_TSN1_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x1A0
/* TSN2 STREAMID */
#define SYSMGR_TSN2_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x1A4
